- Lam’s leadership in 3D NAND built the playbook for memory’s complex architectural transition
- Companies that learn from and apply their experience will lead the way to 3D DRAM
The semiconductor memory industry has been here before.
A little over a decade ago, NAND flash hit a wall. Planar scaling—shrinking features on a flat surface—was running out of physics. Cells got smaller and started interfering with their neighbors, retention degraded, and yields fell. The industry responded by going vertical, stacking memory cells into 3D structures that traded lateral density for vertical capacity. It worked, but the transition was far more demanding than most people outside the fab anticipated.
Today, DRAM is approaching a similar inflection. AI workloads have turned memory bandwidth into the critical system bottleneck, and DRAM manufacturers are pushing planar technology into its sixth generation of 10-nanometer class chips. DRAM makers are exploring new 4F² architectures for sub-10nm era, but reduced cell capacitor and transistor area will push DRAM to device physics limits, requiring DRAM go vertical as well.
We must apply what we learned in the transition to 3D NAND, because in many ways 3D DRAM will be even more complex, more challenging. Learning from history increases the velocity by which we help our customers get ready for the inevitable.
What NAND’s transition required
The popular narrative around 3D NAND focuses on the architecture: stacking dozens, then hundreds, of memory layers into a single structure. What gets less attention is how profoundly that shift changed the manufacturing problem.
Going vertical in NAND meant etching channels through dozens of alternating material layers with extraordinary precision. We had to fill those channels—and the gaps between them—without voids or seams at aspect ratios something the industry had never attempted in volume production. And we had to figure out how to deposit uniform films deep inside structures where conventional chemical vapor deposition couldn’t reach. Every additional layer multiplied the complexity.
Lam established our leadership in this space through ingenuity and precision. Our ALTUS® Halo system, for example, delivers void-free molybdenum fill for the high-aspect-ratio wordlines that 3D NAND requires, replacing tungsten at a point when resistance had become a limiting factor for device performance. Striker®’s atomic layer deposition provides 100% conformal gapfill that vertical architectures need. These new capabilities were developed because the 3D transition created problems that prior generations of equipment could not address.
The broader lesson from NAND is simple: when memory goes vertical, manufacturing intensity increases dramatically. The equipment that enables it determines who can execute the transition at production scale. Lam is a proven partner here.
The parallels to 3D DRAM are real
DRAM’s path toward 3D shares clear similarities with what NAND went through. The physics driving the transition are the same—planar scaling eventually hits limits that vertical stacking can relieve. And the manufacturing implications are familiar: taller structures mean higher aspect ratios, which require more precise etch, more conformal deposition, and more process steps per wafer (what we call deposition and etch intensity).
AI is intensifying the performance, bandwidth, and energy-efficiency requirements DRAM must meet—raising the cost of execution errors and increasing the value of proven process leadership. Modern AI accelerators execute enormous amounts of parallel computation, but they only run at capacity when data arrives fast enough to keep them fed. DRAM is the working memory that does the feeding, and as models grow larger and inference workloads scale , the demand for bandwidth, capacity, and energy efficiency is outpacing what current architectures can deliver. This is the memory wall, and it has become the defining constraint on AI system performance.
That pressure is pulling DRAM’s architectural evolution forward. High-bandwidth memory solutions are already stacking DRAM chips using through-silicon vias, with roadmaps extending to 16 layers by 2028. On the device side, tighter cell layouts and the eventual move to 3D will demand the same kinds of high-aspect-ratio etch, precision deposition, and advanced patterning that defined the NAND transition.
Why DRAM will be more challenging
Here is where the analogy breaks down, and understanding that matters for critical decisions around materials and tool design.
NAND is a storage technology holding “warm and cold” data. When the industry moved to 3D NAND, the primary engineering challenges were structural and materials-related—etch deep enough, fill conformally enough, stack reliably enough. Speed, in the sense of nanosecond-level access times, was not the governing constraint.
DRAM is working memory, constantly written and supplying “hot data” to ultra-fast CPUs and GPUs. DRAM also requires virtually infinite (10^16) cycles of endurance, vs few 1000’s for NAND. Every read and write happens on a timescale that directly affects system performance. When DRAM goes vertical, engineers cannot simply optimize for density and yield. They must maintain signal integrity, minimize latency, and control resistance across stacked layers while simultaneously achieving the structural precision that vertical architectures demand.
That translates to tighter electrical specifications at every level of the stack. Wordline resistance becomes even more critical because signals must travel through more material without degradation. The capacitors storing charge in each cell need to maintain their performance characteristics even as the surrounding geometry changes fundamentally.
There’s a further complication. Unlike NAND, where the industry largely committed to 3D once planar scaling stalled, DRAM manufacturers are actively extending planar technology further than many predicted. The move from 6F² to 4F² meaningfully increases etch, deposition, and patterning intensity while extending planar DRAM’s life. These nodes are not waiting for 3D; they are where Lam is already capturing value today. The same capabilities that win at 4F² compound further as DRAM eventually moves vertical. That duality—supporting today’s most advanced planar nodes and tomorrow’s 3D architectures—is a strategic and engineering challenge we didn’t have to face in the NAND transition.
The velocity of learning
In any major technology transition, the companies that lead aren’t necessarily the ones with the most resources. They’re the ones that learn fastest—the ones that take hard-won knowledge from one problem and apply it to the next before the next problem has fully arrived.
This is what velocity means to us at Lam. Not speed in the colloquial sense, but the rate at which institutional knowledge compounds. The engineers who spent years developing high-aspect-ratio etch for 3D NAND are not starting over when they take on DRAM’s vertical challenges. The process understanding built into Halo’s molybdenum fill for NAND wordlines—barrier-free deposition, void-free performance at extreme aspect ratios—is being adapted for DRAM, where lower resistance at smaller critical dimensions is the priority. Striker’s conformal ALD capabilities, proven in NAND’s gapfill applications, are being extended to address the lateral and vertical fill challenges that 3D DRAM will present.
Velocity is also about proximity. Our engineers work inside customer fabs, which means the feedback loop between a manufacturing challenge and a process solution is measured in days rather than quarters. When customers are pushing sub-10nm planar DRAM and simultaneously evaluating early 3D integration approaches, that closeness compresses development cycles in ways that compound over time.
And it shapes how we bridge both timelines. Akara®’s etch precision, for example, already enables angstrom-level control for transistor formation at advanced planar DRAM nodes, and the same platform is being developed for the ultra-high-aspect-ratio etch that 3D DRAM will require. Aether®’s dry resist technology resolves features below 20 nanometers for current DRAM patterning—capability that maps directly to the tighter geometries of future vertical architectures.
No single tool solves the 3D DRAM challenge. The point is the pattern: develop capabilities against today’s hardest problems and deliberately extend them toward tomorrow’s challenges. That is what separates companies that lead a transition from those that react to one.
What this means for DRAM’s next chapter
As DRAM moves toward more vertical, materials-intensive architectures, the process intensity per wafer rises substantially. More etch steps, more deposition, more patterning complexity—concentrated in the areas where Lam has spent decades building its deepest expertise. We project roughly a 1.7x expansion of our serviceable addressable market per wafer as the industry moves toward 3D. This expansion builds progressively, starting in advanced planar DRAM and increasing further with 3D architectures.
That expansion follows from a technical reality: when memory goes vertical, the equipment that enables precision at extreme dimensions becomes more important, not less. It was true in NAND. It will be true in DRAM.
Lam has already navigated one of the most significant architectural transitions in semiconductor memory history. DRAM’s transition won’t be identical: the specs are tighter, the performance demands are greater, and the need to serve both planar and 3D roadmaps simultaneously introduces complexity the NAND era didn’t impose.
The institutional knowledge we built, the portfolio we developed by solving the hardest problems in memory manufacturing, and the velocity we bring to translating that experience into what comes next matters when confronting a technology inflection. We’re not waiting for 3D DRAM to arrive. We’re already trying to solve it.
